1. Field of the Invention
This application originates from Taiwan patent application No. 84112800 filed Nov. 30, 1995. Said document is incorporated herein by reference.
The present invention relates in general to semiconductor static random access memories (SRAM's). In particular, the present invention relates to an SRAM device having noise elimination circuitry for improving noise immunity during memory access operations.
2. Technical Background
Typical conventional SRAM devices have an electrical circuit schematically shown in the block diagram of FIG. 1. An SRAM device comprises primarily a memory cell array 11 that includes cells arranged in rows and columns. In addition to the memory cell array 11, the typical SRAM device may further include a row address decoder 12, a column address decoder 13, an address buffer 14, an access control pulse generator 15, a sense amplifier 16, an address transition detector (ATD) 17, an output buffer 18, and an I/O port 19.
Notice that FIG. 1 only schematically shows the structural block diagram of the typical SRAM device in its read mode, therefore, only an output buffer 18 is shown therein. During such memory read cycles, while data stored in the memory cell array 11 may be read out, data can also be written into the memory cell array 11 in write cycles in the reverse direction of read data flow, as persons skilled in this art may be well aware.
The memory cell array 11 is itself comprised typically of hundreds of thousands of memory cells 110 orderly arranged in an array of rows and columns. Whenever memory access to the SRAM device is desired, that is, data are either read out from or written into the array 11, an external memory controller not shown in the drawing issues an access address XA via the peripheral address bus 10. The access address is then buffered in the address buffer 14 and decoded by both the row address decoder 12 and column address decoder 13 to obtain the row and column addresses respectively. Based on this pair of row and column addresses, the desired data may be either retrieved or stored in the correct location inside the memory cell array 11.
The relative timing sequence of the various components in the SRAM device of FIG. 1 is shown in the timing diagram of FIG. 2. With simultaneous reference to FIGS. 1 and 2, when a typical read access cycle performed against the SRAM device of FIG. 1 is initiated, the access address XA is sent by the memory controller via the peripheral address bus 10 to the address buffer 14 for temporary storage during the cycle. Whenever any bit of the access address XA is detected by the address transition detector 17 to have undergone a logical state transition 21, the address transition detector 17 will then issue a relatively short pulse 22 to the access control pulse generator 15. Upon detecting the trailing edge of the short pulse 22 generated by the address transition detector 17, the access control pulse generator 15 may then generate and send a word line enable signal WLE 23 and a sense amplifier enable signal SAE 24 to the row address decoder 12 and the sense amplifier 16 respectively.
Word line enable signal WLE 23 may be employed by the row decoder 12 to turn on the corresponding word line WL in the memory cell array 11 for a predetermined short time period 25. On the other hand, the sense amplifier enable signal SAE 24 allows the sense amplifier 16 to be enabled almost at the same time when the selected word line WL is turned on for the period 25. When the selected word line remains turned on, the data stored in the very memory cell corresponding to the access address XA appears on a corresponding pair of bit lines BL and BLB as a voltage difference 26. This voltage difference 26 which represents the stored data that is to be read in the discussed SRAM read cycle may then be sensed by an amplifier and read out by the circuitry of the column decoder 13. Sense amplifier 16 subsequently amplifies this data signal to convert it into the data 27 having an appropriate voltage level which is then sent to the output buffer 18 and latched. The data in the output buffer 18 is then relayed to the I/O port 19 for supply to the logics exterior of the SRAM device that requested for the data.
When the sense amplifier enable pulse SAE is terminated as is seen in FIG. 2, the sense amplifier 16 will be disabled, and its output turned off accordingly. However, since the read data has already been latched in the output buffer 18, the accessed data in the very SRAM read cycle may thus be maintained for a time period sufficient to meet the requirements of the data requesting logics in the system.
In these conventional SRAM devices, when the word line enable pulse WLE is terminated, all the word lines in the memory cell array 11 will be turned off as well. No unnecessary power dissipation will take place in any memory cell unit in the array as a result of any word line being left turned on. The overall power consumption of the SRAM device can therefore be minimized as much as possible.
In those general environments for the application of these conventional SRAM devices, however, there are the possibilities that unexpected noise signals arise to interfere with the read cycle operations. Such noise signals may cause erroneous actions of the constituent components of the SRAM device that result in the presence of erroneous data in the I/O port of the memory device. FIG. 3 of the drawing, for example, shows the conventional SRAM device of FIG. 1 conducting a read access cycle that is interfered with by the occurrence of a noise pulse.
The noise interference situation as exemplified in FIG. 3 is caused by a noise pulse 31. The pulse 31 occurs amongst the bits of the access address XA and causes address transition detector 17 to generate a short pulse 32 having a time period much shorter than its normal pulse. This short pulse 32 triggered as a result of the presence of the noise in the memory access address bits causes the access control pulse generator 15 to issue a short WLE pulse 33 and SAE pulse 34 to row decoder 12 and sense amplifier 16 respectively. Although such noise-triggered SAE pulses 34 would generally have a very short time period, it is, however, still possible for this period to be sufficiently long enough to enable the functioning of the sense amplifier 16. Once the sense amplifier 16 is enabled without the word line WL properly turned on as signified by the low pulse 35, random erroneous data 37 may still occur. This noise-triggered erroneous data 37 would be undesirably latched by the output buffer 18 and subsequently conveyed via the I/O port 19 to the exterior logics.